Renesas R61509V User Manual

Rev. 0.11 April 25, 2008, page 1 of 181 Target Spec R61509V 260k-color, 240RGB x 432-dot graphics liquid crystal controller driver for Amorph

R61509V Target Spec Rev. 0.11 April 25, 2008, page 10 of 181 Block Diagram 㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷㩷 㩷㩷㩷㩷㩷㩷㩷㩷VCCVDD㩷㩷㩷㩷C13P/C13MG1-G432 VGHVGL㩷 㩷㩷㩷㩷

R61509V Target Spec Rev. 0.11 April 25, 2008, page 100 of 181 80-System 18-bit Bus Interface A1HWRRSWRX18R61509V HOST PROCESSORIM[2:0] = 0

R61509V Target Spec Rev. 0.11 April 25, 2008, page 101 of 181 80-System 16-bit Bus Interface A1HWRRSWR:16R61509VHOSTPROCESSORIM[2:0] = 010C

R61509V Target Spec Rev. 0.11 April 25, 2008, page 102 of 181 1DB 17 DB6DB 5 DB14 DB13 DB12DB11DB10DB8DBDB6DB5DB4 DB3 DB2 DB1R5 R4 R3 R2

R61509V Target Spec Rev. 0.11 April 25, 2008, page 103 of 181 Data Transfer Synchronization in 16-bit Bus Interface Operation The R61509V s

R61509V Target Spec Rev. 0.11 April 25, 2008, page 104 of 181 80-System 9-bit Bus Interface When transferring 16-bit instruction, it is div

R61509V Target Spec Rev. 0.11 April 25, 2008, page 105 of 181 DB 17 DB16DB 15 DB14 DB13 DB12DB11DB10DB9DB17DB6DB5DB14DB13 DB12 DB11 DB10

R61509V Target Spec Rev. 0.11 April 25, 2008, page 106 of 181 80-System 8-bit Bus Interface When transferring 16-bit instruction, it is div

R61509V Target Spec Rev. 0.11 April 25, 2008, page 107 of 181 DB 17 DB16DB 15 DB14 DB13 DB12DB11DB10DB17DB16DB15DB14DB13 DB12 DB11 DB10 R

R61509V Target Spec Rev. 0.11 April 25, 2008, page 108 of 181 Data Transfer Synchronization in 8-bit Bus Interface operation The R61509V su

R61509V Target Spec Rev. 0.11 April 25, 2008, page 109 of 181 Serial Interface The serial interface is selected by setting the IM2/1 pins

R61509V Target Spec Rev. 0.11 April 25, 2008, page 11 of 181 Block Function 1. System Interface The R61509V supports 80-system high-speed i

R61509V Target Spec Rev. 0.11 April 25, 2008, page 110 of 181 First transfer (upper) Secon d t ransfer (lower)D15D14D13D12D11D10D9 D8 D7 D6

R61509V Target Spec Rev. 0.11 April 25, 2008, page 111 of 181 D0LSB1“0” “1” “1” “1” “0” ID RS RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4

R61509V Target Spec Rev. 0.11 April 25, 2008, page 112 of 181 VSYNC Interface The R61509V supports VSYNC interface, which enables displayin

R61509V Target Spec Rev. 0.11 April 25, 2008, page 113 of 181 The VSYNC interface has the minimum for RAM data write speed and internal clo

R61509V Target Spec Rev. 0.11 April 25, 2008, page 114 of 181 RAMwriteDisplay operation016.67(60 Hz)Back porch (14 lines)Main panelMoving p

R61509V Target Spec Rev. 0.11 April 25, 2008, page 115 of 181 3. The front porch period continues from the end of one frame period to the

R61509V Target Spec Rev. 0.11 April 25, 2008, page 116 of 181 FMARK Interface In the FMARK interface operation, data is written to interna

R61509V Target Spec Rev. 0.11 April 25, 2008, page 117 of 181 When transferring data in synchronization with FMARK signal, minimum RAM data

R61509V Target Spec Rev. 0.11 April 25, 2008, page 118 of 181 starts the display operation of the data written in that line and can write m

R61509V Target Spec Rev. 0.11 April 25, 2008, page 119 of 181 Table 60 Table 61 FMP[8:0] FMARK output position

R61509V Target Spec Rev. 0.11 April 25, 2008, page 12 of 181 Table 4 IM2 IM1 IM0 System interface DB pins RAM write data Instruction w

R61509V Target Spec Rev. 0.11 April 25, 2008, page 120 of 181 FMP Setting Example NL=6'h35 Front porchDisplay areaFMP=9’h008NL=6’h35 (

R61509V Target Spec Rev. 0.11 April 25, 2008, page 121 of 181 RGB Interface The R61509V supports the RGB interface. The interface format i

R61509V Target Spec Rev. 0.11 April 25, 2008, page 122 of 181 Polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK Signals The polarities of VS

R61509V Target Spec Rev. 0.11 April 25, 2008, page 123 of 181 Setting Example of Display Control Clock in RGB Interface Operation Register

R61509V Target Spec Rev. 0.11 April 25, 2008, page 124 of 181 RGB Interface Timing The timing relationship of signals in RGB interface oper

R61509V Target Spec Rev. 0.11 April 25, 2008, page 125 of 181 Moving Picture Display via RGB Interface The R61509V supports RGB interface f

R61509V Target Spec Rev. 0.11 April 25, 2008, page 126 of 181 16-Bit RGB Interface The 16-bit RGB interface is selected by setting RIM = 1

R61509V Target Spec Rev. 0.11 April 25, 2008, page 127 of 181 18-bit RGB Interface The 18-bit RGB interface is selected by setting RIM = 0

R61509V Target Spec Rev. 0.11 April 25, 2008, page 128 of 181 Notes to RGB Interface Operation 1. The following functions are not availabl

R61509V Target Spec Rev. 0.11 April 25, 2008, page 129 of 181 RAM Address and Display Position on the Panel The R61509V has memory to store

R61509V Target Spec Rev. 0.11 April 25, 2008, page 13 of 181 4. Graphics RAM (GRAM) GRAM stands for graphics RAM, which can store bit-patt

R61509V Target Spec Rev. 0.11 April 25, 2008, page 130 of 181 (VSA,VEA) 9’h0009’h1AFNL(HSA,HEA) Window AddressPTDP1PTSA0PTEA0䇼LCD䇽Panel dis

R61509V Target Spec Rev. 0.11 April 25, 2008, page 131 of 181 The following figure shows the relationship among the RAM address, display po

R61509V Target Spec Rev. 0.11 April 25, 2008, page 132 of 181 Instruction Setting Example The followings are examples of settings for 240(R

R61509V Target Spec Rev. 0.11 April 25, 2008, page 133 of 181 2. Partial only The following is an example of settings for displaying partia

R61509V Target Spec Rev. 0.11 April 25, 2008, page 134 of 181 Window Address Function The window address function enables writing display d

R61509V Target Spec Rev. 0.11 April 25, 2008, page 135 of 181 Scan Mode Setting The R61509V can set the gate pin assignment and the scan di

R61509V Target Spec Rev. 0.11 April 25, 2008, page 136 of 181 8-Color Display Mode The R61509V has a function to display in eight colors.

R61509V Target Spec Rev. 0.11 April 25, 2008, page 137 of 181 Frame-Frequency Adjustment Function The R61509V supports a function to adjust

R61509V Target Spec Rev. 0.11 April 25, 2008, page 138 of 181 Under the above conditions, the frame frequency can be changed according to t

R61509V Target Spec Rev. 0.11 April 25, 2008, page 139 of 181 Partial Display Function The partial display function allows the R61509V to d

R61509V Target Spec Rev. 0.11 April 25, 2008, page 14 of 181 Pin Function Table 5 External Power Supply Signal I/O Connect to Functio

R61509V Target Spec Rev. 0.11 April 25, 2008, page 140 of 181 Liquid Crystal Panel Interface Timing The relationships between RGB interface

R61509V Target Spec Rev. 0.11 April 25, 2008, page 141 of 181 RGB Interface Operation 1 2 3 4 5 6 432431430 1

R61509V Target Spec Rev. 0.11 April 25, 2008, page 142 of 181 γ Correction Function γ Correction Function The R61509V supports γ-correction

R61509V Target Spec Rev. 0.11 April 25, 2008, page 143 of 181 γ Correction Registers The γ-correction registers include 42 bits for each of

R61509V Target Spec Rev. 0.11 April 25, 2008, page 144 of 181 Table 71 Reference Level Adjustment Registers and Resistors Register Registe

R61509V Target Spec Rev. 0.11 April 25, 2008, page 145 of 181 Interpolation Registers Table 72 Interpolation Registers Gamma Control Inte

R61509V Target Spec Rev. 0.11 April 25, 2008, page 146 of 181 Table 74 Interpolation Factor for V56 to V61 PI0*3[1:0] PI0*2[1:0] IPV56 I

R61509V Target Spec Rev. 0.11 April 25, 2008, page 147 of 181 Table 75 Grayscale Voltage Calculation Formula Grayscale voltage Formula Gray

R61509V Target Spec Rev. 0.11 April 25, 2008, page 148 of 181 Frame Memory Data and the Grayscale Voltage Table 76 Grayscale Voltage Gr

R61509V Target Spec Rev. 0.11 April 25, 2008, page 149 of 181 Power Supply Generating Circuit The following figures show the configurations

R61509V Target Spec Rev. 0.11 April 25, 2008, page 15 of 181 DB[17:0] I/O Host processor 18-bit parallel bi-directional data bus for 80-sys

R61509V Target Spec Rev. 0.11 April 25, 2008, page 150 of 181 Power Supply Circuit Connection Example 2 (VCI1 = VCI Direct Input) In the fo

R61509V Target Spec Rev. 0.11 April 25, 2008, page 151 of 181 Specifications of Power-supply Circuit External Elements The specifications o

R61509V Target Spec Rev. 0.11 April 25, 2008, page 152 of 181 Voltage Setting Pattern Diagram The following are the diagrams of voltage gen

R61509V Target Spec Rev. 0.11 April 25, 2008, page 153 of 181 Liquid Crystal Application Voltage Waveform and Electrical Potential VCOM Gn

R61509V Target Spec Rev. 0.11 April 25, 2008, page 154 of 181 VCOMH and VREG1OUT Voltage Adjustment Sequence When adjusting the VCOMH volta

R61509V Target Spec Rev. 0.11 April 25, 2008, page 155 of 181 NVM Control The R61509V incorporates 16-bit NVM for user’s use. • 7 bits a

R61509V Target Spec Rev. 0.11 April 25, 2008, page 156 of 181 NVM Load (Register Resetting) Sequence Data on the NVM is loaded either autom

R61509V Target Spec Rev. 0.11 April 25, 2008, page 157 of 181 NVM Write Sequence Defined 16 bit data is written to the selected address. W

R61509V Target Spec Rev. 0.11 April 25, 2008, page 158 of 181 NVM Erase Sequence The data written to the selected 16 bits is erased all tog

R61509V Target Spec Rev. 0.11 April 25, 2008, page 159 of 181 Power Supply Setting Sequence The following are the sequences for setting pow

R61509V Target Spec Rev. 0.11 April 25, 2008, page 16 of 181 PROTECT I Host processor Reset protect pin. The R61509V enters a reset protec

R61509V Target Spec Rev. 0.11 April 25, 2008, page 160 of 181 ޣᶧ᥏㔚ḮࠝࡈࡈࡠޤR102h: PON=0 PSON=0 㪞㪥㪛Power Supply OFF Sequence5 frames or mor

R61509V Target Spec Rev. 0.11 April 25, 2008, page 161 of 181 Notes to Power Supply ON Sequence When voltages do not rise in the order of V

R61509V Target Spec Rev. 0.11 April 25, 2008, page 162 of 181 Instruction Setting Sequence and Refresh Sequence Display ON/OFF Sequences an

R61509V Target Spec Rev. 0.11 April 25, 2008, page 163 of 181 Shutdown Mode Sequences CSX=”Low” (1)CSX=”Low” (2)CSX=”Low” (3)CSX=”Low” (4)C

R61509V Target Spec Rev. 0.11 April 25, 2008, page 164 of 181 Index Write (Data=16’h0000)Index Write (Data=16’h0000)Index Write (Data=16’h0

R61509V Target Spec Rev. 0.11 April 25, 2008, page 165 of 181 Index Write (Data=8’h00)Index Write (Data=8’h00)Index Write (Data=8’h00)Inde

R61509V Target Spec Rev. 0.11 April 25, 2008, page 166 of 181 8-Color Mode Setting R00Bh: COL=1262,144-color modedisplay8-color mode displa

R61509V Target Spec Rev. 0.11 April 25, 2008, page 167 of 181 Absolute Maximum Ratings Table 82 Notes: 1. If used beyond the absolute ma

R61509V Target Spec Rev. 0.11 April 25, 2008, page 168 of 181 Electrical Characteristics DC Characteristics (VCC= 2.50V~3.30V, VCI=2.50V~3.

R61509V Target Spec Rev. 0.11 April 25, 2008, page 169 of 181 LCD power supply current (VCI-GND) 8-color, 64-line partial display Ici2 mA

R61509V Target Spec Rev. 0.11 April 25, 2008, page 17 of 181 Table 8 LCD drive Signal I/O Connect to Function When not in use VREG1OUT O S

R61509V Target Spec Rev. 0.11 April 25, 2008, page 170 of 181 Step-up Circuit Characteristics Table 84 Item Unit Test condition Min. Typ.

R61509V Target Spec Rev. 0.11 April 25, 2008, page 171 of 181 Power Supply Voltage Range (Ta= -40°C~+85°C, GND=AGND=0V) Table 86 Item Symbo

R61509V Target Spec Rev. 0.11 April 25, 2008, page 172 of 181 AC Characteristics (VCC= 2.50V~3.30V, IOVCC=1.65V~3.30V, Ta= -40°C~+85°C *See

R61509V Target Spec Rev. 0.11 April 25, 2008, page 173 of 181 Clock Synchronous Serial Interface Timing Characteristics (IOVCC=1.65V~3.30V

R61509V Target Spec Rev. 0.11 April 25, 2008, page 174 of 181 LCD Driver Output Characteristics Table 92 Item Symbol Unit Test condition

R61509V Target Spec Rev. 0.11 April 25, 2008, page 175 of 181 Notes to Electrical Characteristics Note 1. The DC/AC electrical characteris

R61509V Target Spec Rev. 0.11 April 25, 2008, page 176 of 181 Note 3: Test 1, 2 and 3 pins must be grounded. The VDDTEST and VREFC must be

R61509V Target Spec Rev. 0.11 April 25, 2008, page 177 of 181 Timing Characteristics 80-system Bus Interface tDDR tDHRVILVOLtWRfVIH VIL VI

R61509V Target Spec Rev. 0.11 April 25, 2008, page 178 of 181 Clock Synchronous Serial Interface VILVILVILVILVILtscrVIL VIH CSXtSCYCVIH S

R61509V Target Spec Rev. 0.11 April 25, 2008, page 179 of 181 RGB Interface tPDH VIL VIH VIL VIH VIL VILVSYNCX HSYNCX VIH VIH VIL ENABLE VI

R61509V Target Spec Rev. 0.11 April 25, 2008, page 18 of 181 Table 9 Others (test, dummy pins) Signal I/O Connect to Function When not in u

Keep safety rst in your circuit designs!1. Renesas Technology Corp. puts the maximum eort into making semiconductor products better and more reliabl

R61509V Target Spec Rev. 0.11 April 25, 2008, page 181 of 181 Revision Record Rev. Date Page No. Contents of Modification Drawn by Appro

R61509V Pad Arrangement Rev 0.6(1-a)NoNo □ DUMMYR4 1434□ DUMMYR3 1433□ TESTO15 14321 DUMMYR1 □ □ VGLDMY4 14312 DUMMYR2 □ □ G1 14303 AGNDDUM1 □ □ G3 1

R61509V Target Spec Rev. 0.11 April 25, 2008, page 2 of 181 Outline ...

R61509V Target Spec Rev. 0.11 April 25, 2008, page 20 of 181 ●Chip size: 19.03mm x 0.76mm ●Chip thickness: 280μm (typ) ●Pad coordinates: P

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y1 DUMMYR1 -9135.0 -269.0 51 TS5 -5635.0 -269.02 DUMMYR2 -9065.

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y101 GNDDUM8 -2135.0 -269.0 151 GND 1365.0 -269.0102 DB3 -2065.

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y201 VCI 4865.0 -269.0 251 C21M 8365.0 -269.0202 VCI 4935.0 -26

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y301 G70 8827.5 157.0 351 G170 8077.5 157.0302 G72 8812.5 276.0

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y401 G270 7327.5 157.0 451 G370 6577.5 157.0402 G272 7312.5 276

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y501 S704 5632.5 276.0 551 S654 4882.5 276.0502 S703 5617.5 157

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y601 S604 4132.5 276.0 651 S554 3382.5 276.0602 S603 4117.5 157

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y701 S504 2632.5 276.0 751 S454 1882.5 276.0702 S503 2617.5 157

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y801 S404 1132.5 276.0 851 TESTO12 -457.5 276.0802 S403 1117.5

R61509V Target Spec Rev. 0.11 April 25, 2008, page 3 of 181 NVM Control ...

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y901 S312 -1207.5 276.0 951 S262 -1957.5 276.0902 S311 -1222.5

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y1001 S212 -2707.5 276.0 1051 S162 -3457.5 276.01002 S211 -2722

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y1101 S112 -4207.5 276.0 1151 S62 -4957.5 276.01102 S111 -4222.

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y1201 S12 -5707.5 276.0 1251 G359 -6652.5 157.01202 S11 -5722.5

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y pad No pad name X Y1301 G259 -7402.5 157.0 1351 G159 -8152.5 157.01302 G257 -7417

R61509V Pad Coordinate （Unit：μm）2008.04.21 rev0.1pad No pad name X Y X Y1401 G59 -8902.5 157.0 -9381.0 -251.01402 G57 -8917.5 276.0 9381.0 -251.01403

R61509V Target Spec Rev. 0.11 April 25, 2008, page 36 of 181 Bump Arrangement 㪪㪪㪈䌾㪪㪎㪉㪇䋬㩷㪞㪈䌾㪞㪋㪊㪉䋬㩷㪛㪬㪤㪤㪰㪩㪎㪄㪈㪇㪃㩷㪫㪜㪪㪫㪦㪈㪈㪄㪈㪏㪃㩷㪭㪞㪣㪛㪤㪰㪈㪄㪋㩷㩷㩷㩷㩷㩷㩷

R61509V Wiring Example & Recommended Wiring Resistance(Pad Arrangement Rev0.6) 2008.04.21　Rev0.5VCOMR61509V Pad name□ DUMMYR41 DUMMYR1 □ DUMMYR32

R61509V Target Spec Rev. 0.11 April 25, 2008, page 38 of 181 GRAM Address Map Table 11 GRAM address and display position on the panel (SS

R61509V Target Spec Rev. 0.11 April 25, 2008, page 39 of 181 Table 12 GRAM address and display position on the panel (SS = 1, BGR = 1) S/G

R61509V Target Spec Rev. 0.11 April 25, 2008, page 4 of 181 Partial Display Function ...

R61509V Target Spec Rev. 0.11 April 25, 2008, page 40 of 181 Instruction Outline The R61509V adopts 18-bit bus architecture in order to int

R61509V Target Spec Rev. 0.11 April 25, 2008, page 41 of 181 Index (IR) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3

R61509V Target Spec Rev. 0.11 April 25, 2008, page 42 of 181 LCD Drive Wave Control (R002h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8

R61509V Target Spec Rev. 0.11 April 25, 2008, page 43 of 181 BGR: Reverses the order from RGB to BGR in writing 18-bit pixel data in the GR

R61509V Target Spec Rev. 0.11 April 25, 2008, page 44 of 181 ORG = 0AM = 0HorizontalAM = 1VerticalID1-0 =

R61509V Target Spec Rev. 0.11 April 25, 2008, page 45 of 181 Display Control 1 (R007h) BASEE: Base image display enable bit. BASEE = 0: No

R61509V Target Spec Rev. 0.11 April 25, 2008, page 46 of 181 Display Control 2 (R008h) FP[7:0]: Sets the number of lines for front porch p

R61509V Target Spec Rev. 0.11 April 25, 2008, page 47 of 181 VSYNCXNLBPFPBack porch Front porch Display AreaNote: The output timing to the

R61509V Target Spec Rev. 0.11 April 25, 2008, page 48 of 181 Display Control 3 (R009h) PTS: Sets the source output level to drive non-disp

R61509V Target Spec Rev. 0.11 April 25, 2008, page 49 of 181 8 Color Control (R00Bh) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6

R61509V Target Spec Rev. 0.11 April 25, 2008, page 5 of 181 Clock Characteristics ...

R61509V Target Spec Rev. 0.11 April 25, 2008, page 50 of 181 External Display Interface Control 1 (R00Ch) RIM: Sets the interface format w

R61509V Target Spec Rev. 0.11 April 25, 2008, page 51 of 181 ENC[2:0]: Sets the RAM write cycle via RGB interface. Table 21 ENC[2:0] RAM

R61509V Target Spec Rev. 0.11 April 25, 2008, page 52 of 181 External Display Interface Control 2 (R00Fh) R/W RS IB15 IB14 IB13 IB12 IB1

R61509V Target Spec Rev. 0.11 April 25, 2008, page 53 of 181 Panel Interface Control 1 (R010h) RTNI[4:0]: Sets 1H (line) period. This se

R61509V Target Spec Rev. 0.11 April 25, 2008, page 54 of 181 Frame Frequency Calculation fosc Frame frequency = Clocks per line x division

R61509V Target Spec Rev. 0.11 April 25, 2008, page 55 of 181 Panel Interface Control 2 (R011h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9

R61509V Target Spec Rev. 0.11 April 25, 2008, page 56 of 181 Panel Interface Control 3 (R012h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8

R61509V Target Spec Rev. 0.11 April 25, 2008, page 57 of 181 SEQWI[2:0]: Sets source equalize period. SEQWI setting is enabled only when t

R61509V Target Spec Rev. 0.11 April 25, 2008, page 58 of 181 Panel Interface Control 4 (R013h) MCPI: Defines VCOM alternating timing. Thi

R61509V Target Spec Rev. 0.11 April 25, 2008, page 59 of 181 Panel Interface Control 5 (R014h) PCDIVH[2:0], PCDIVL[2:0]: When DM=1 and RGB

R61509V Target Spec Rev. 0.11 April 25, 2008, page 6 of 181 Description The R61509V is a single-chip liquid crystal controller driver LSI f

R61509V Target Spec Rev. 0.11 April 25, 2008, page 60 of 181 Panel Interface Control 6 (R020h) DIVE[1:0]: Sets the division ratio of DOTCL

R61509V Target Spec Rev. 0.11 April 25, 2008, page 61 of 181 RTNE[5:0]: Sets RTNE in combination with PCDIVH and PCDIVL to decide the numbe

R61509V Target Spec Rev. 0.11 April 25, 2008, page 62 of 181 Panel Interface Control 7 (R021h) NOWE[2:0]: Sets the non-overlap period of a

R61509V Target Spec Rev. 0.11 April 25, 2008, page 63 of 181 Panel Interface Control 8 (R022h) VEQWE[2:0]: Sets low power VCOM drive perio

R61509V Target Spec Rev. 0.11 April 25, 2008, page 64 of 181 SEQWE[2:0]: Sets source equalize period. SEQWE setting is enabled when the R6

R61509V Target Spec Rev. 0.11 April 25, 2008, page 65 of 181 Panel Interface Control 9 (R023h) MCPE [2:0]: Specifies VCOM alternating poin

R61509V Target Spec Rev. 0.11 April 25, 2008, page 66 of 181 Frame Marker Control (R090h) FMI[2:0]: Sets FMARK output interval by FMI regi

R61509V Target Spec Rev. 0.11 April 25, 2008, page 67 of 181 Power Control Power Control 1 (R100h) DSTB: When DSTB = 1, the R61509V enter

R61509V Target Spec Rev. 0.11 April 25, 2008, page 68 of 181 BT[2:0]: Sets the factor used in the step-up circuits. Select the optimal ste

R61509V Target Spec Rev. 0.11 April 25, 2008, page 69 of 181 Power Control 2 (R101h) DC1 [2:0]: Sets step-up clock frequency for Step-up

R61509V Target Spec Rev. 0.11 April 25, 2008, page 7 of 181 Features • A single-chip controller driver incorporating a gate circuit and a p

R61509V Target Spec Rev. 0.11 April 25, 2008, page 70 of 181 DC0 [2:0]: Sets step-up clock frequency for Step-up Circuit 1. The step-up cl

R61509V Target Spec Rev. 0.11 April 25, 2008, page 71 of 181 VC[2:0]: Sets VCI voltage level. VC[2:0] VCI1 voltage (Reference voltage for

DC0ｘ Value and DCDC1 Step-up Clock Signal Waveform Example DCDC1 performs charge operation and boost operation with the step-up clock generated from

R61509V Target Spec Rev. 0.11 April 25, 2008, page 73 of 181 Power Control3 (R102h) Note: True values of PSON and PON are not read when ins

R61509V Target Spec Rev. 0.11 April 25, 2008, page 74 of 181 Power Control 4 (R103h) VDV[4:0]: Selects the factor of VREG1OUT to set the am

R61509V Target Spec Rev. 0.11 April 25, 2008, page 75 of 181 RAM Access RAM Address Set (Horizontal Address) (R200h) RAM Address Set (Verti

R61509V Target Spec Rev. 0.11 April 25, 2008, page 76 of 181 GRAM Data Write (R202h) R/W RS W 1 RAM write data WD[17:0] is

R61509V Target Spec Rev. 0.11 April 25, 2008, page 77 of 181 GRAM Data Read (R202h) R/W RS R 1 RAM read data RD[17:0] is t

R61509V Target Spec Rev. 0.11 April 25, 2008, page 78 of 181 NVM Data Read / NVM Data Write (R280h) UID[3:0]: Used to temporarily store N

R61509V Target Spec Rev. 0.11 April 25, 2008, page 79 of 181 Table 48 VCM [6:0] VCOMH voltage VCM [6:0] VCOMH voltage 7’h00 VREG1O

R61509V Target Spec Rev. 0.11 April 25, 2008, page 8 of 181 Power Supply Specifications Table 1 No. Item R61509V 1 TFT data lines 720 ou

R61509V Target Spec Rev. 0.11 April 25, 2008, page 80 of 181 7’h38 VREG1OUT x 0.716 7’h78 VREG1OUT x 0.972 7’h39 VREG1OUT x 0.720

R61509V Target Spec Rev. 0.11 April 25, 2008, page 81 of 181 Window Address Control Window Horizontal RAM Address Start (R210h), Window Ho

R61509V Target Spec Rev. 0.11 April 25, 2008, page 82 of 181 γ Control γ Control 1 ~ 14 (R300h to R309h) R/W RS IB15 IB14 IB13 IB1

R61509V Target Spec Rev. 0.11 April 25, 2008, page 83 of 181 PR0P00[4:0] PR0N00[4:0] Adjusts reference level for positive polarity output

R61509V Target Spec Rev. 0.11 April 25, 2008, page 84 of 181 Base Image Display Control Base Image Number of Line (R400h) Base Image Displa

R61509V Target Spec Rev. 0.11 April 25, 2008, page 85 of 181 Table 50 VLE Base image 0 Fixed 1 Scrolling enabled REV: Grayscale level of

R61509V Target Spec Rev. 0.11 April 25, 2008, page 86 of 181 Table 53 NL [5:0] Number of drive line NL [5:0] Number of drive line 6’h00

R61509V Target Spec Rev. 0.11 April 25, 2008, page 87 of 181 Table 54 Gate scan start position SM=0 SM=1 SCN[5:0] GS=0 GS=1 GS=0 GS=1 6’h0

R61509V Target Spec Rev. 0.11 April 25, 2008, page 88 of 181 Partial Display Control Partial Image 1: Display Position (R500h), RAM Address

R61509V Target Spec Rev. 0.11 April 25, 2008, page 89 of 181 Pin Control Test Register (Software Reset) (R600h) TRSR: When TRSR = 1, test

Difference Between R61509 and R61509V 2008.04.18Index Command Code Function R61509 R61509V(Pin) System InterfaceIM2-0=011, TRI=1, DFM=0 8bit 3 transf

R61509V Target Spec Rev. 0.11 April 25, 2008, page 90 of 181 NVM Control NVM Access Control 1 (R6F0h), NVM Access Control 2 (R6F1h), NVM A

R61509V Target Spec Rev. 0.11 April 25, 2008, page 91 of 181 R6F1hWrite data to NVM(NVM) Read data from NVMR280hWrite “1” to NVDAT[15]. 㪥㪭㩷

●R61509V　Instruction List Rev 0.50 2008. 04. 22Middle category Upper Index Index Command IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 I

R61509V Target Spec Rev. 0.11 April 25, 2008, page 93 of 181 Reset Function The R61509V is initialized by the RESETX input. During reset p

R61509V Target Spec Rev. 0.11 April 25, 2008, page 94 of 181 5 When a RESETX input is entered into the R61509V while it is in shutdown mo

R61509V Target Spec Rev. 0.11 April 25, 2008, page 95 of 181 Basic Mode Operation of the R61509V The basic operation modes of the R61509V a

R61509V Target Spec Rev. 0.11 April 25, 2008, page 96 of 181 Interface and Data Format The R61509V supports system interface for making ins

R61509V Target Spec Rev. 0.11 April 25, 2008, page 97 of 181 CSXRSWRXR61509VSystem interface18/16/9/8RGB interface18/16DB17-0(RDX)ENABLEVSY

R61509V Target Spec Rev. 0.11 April 25, 2008, page 98 of 181 RGB interface operation (2) This mode enables the R61509V to rewrite RAM data

R61509V Target Spec Rev. 0.11 April 25, 2008, page 99 of 181 System Interface The following are the kinds of system interfaces available wi