Renesas M65881AFP User Manual

Rev.1.00 2003.05.08 page 1 of 23Digital Amplifier Processor of S-Master* TechnologyM65881AFPREJ03F0004-0100ZRev.1.002003.05.08DESCRIPTIONThe M65881A

Rev.1.00 2003.05.08 page 10 of 23M65881AFPOUTL1, OUTL2, OUTR1 and OUTR2 are pulse output modulated ∆Σ output to PWM signal. These pins are connected

Rev.1.00 2003.05.08 page 11 of 23M65881AFPHPOUTL1, HPOUTL2, HPOUTR1 and HPOUTR2 are output pins for Headphone output.PWM output modulated ∆Σ output d

Rev.1.00 2003.05.08 page 12 of 23M65881AFP13. Power sequencesSystem power-on sequencing * Refer to following figure.XXXXXPower(Vddxxx, HPVddxxx,XVdd

Rev.1.00 2003.05.08 page 13 of 23M65881AFPSERIAL CONTROLbit Flag name Functional Explanation H L INIT1 MODE1 Mode setting1 "L" fixed–2 MODE

Rev.1.00 2003.05.08 page 14 of 23M65881AFPThe index and Mantissa part of Gain Data (bit12-bit24 :GAIN0-GAIN12)The gain value is set from bit12-bit24.

Rev.1.00 2003.05.08 page 15 of 23M65881AFP• Soft MuteThe Soft Mute function is executed by setting of Gain Data as 00000/00000000b(" / " me

Rev.1.00 2003.05.08 page 16 of 23M65881AFPTable 2-1 Selection of input formatTable 2-2 Setting for Input Data Word LengthTable 2-3 Selection of Inp

Rev.1.00 2003.05.08 page 17 of 23M65881AFPFs Selection for De-emphasis filter (De-emphasis is "ON" except for bit9="L" and bit10

Rev.1.00 2003.05.08 page 18 of 23M65881AFP3. System2 ModeNo setting bits means "Don't care".Table 3-1 DC dithering selection at ∆Σ blo

Rev.1.00 2003.05.08 page 19 of 23M65881AFPFlag to " Enable " of Asynchronous Detection for secondary block ( bit8: ASYNCEN2)ASYNCEN2 (bit8

Rev.1.00 2003.05.08 page 2 of 23M65881AFPPIN CONFIGURATIONVddLVssRVssLOUTL2XOVddXfsoOUTXOVssDVddDVssMCKSELSCDTSCSHIFTSCLATCHNSPMUTEINITLRCKBCKDATABFV

Rev.1.00 2003.05.08 page 20 of 23M65881AFPAC CHARACTERISTICS(Ta=25ºC, PWMVdd=3.3V, DVdd=1.8V)AC CHARACTERISTICS TIMING CHART(1)XfsoIN, XfsiIN Duty Ra

Rev.1.00 2003.05.08 page 21 of 23M65881AFPAPPLICATION EXAMPLELow Pass Filter/Headphone AmplifierInput Mode Select1Secondary synchronized clock (For M

Rev.1.00 2003.05.08 page 22 of 23M65881AFPDETAILED DIAGRAM OF PACKAGE OUTLINESSOP42-P-450-0.80Weight(g)––JEDEC CodeEIAJ Package CodeLead MaterialCu A

Rev.1.00 2003.05.08 page 23 of 23M65881AFPCopyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.http://www.renesas.

Rev.1.00 2003.05.08 page 3 of 23M65881AFPBLOCK DIAGRAMMCKSELFsoCKOFsoIXfsoOUTXfsoINSFLAGOUTR1OUTL1OUTR2OUTL2SamplingRate ConverterGain ControlDATABCK

Rev.1.00 2003.05.08 page 4 of 23M65881AFPABSOLUTE MAXIMUM RATINGSRECOMMENDED OPERATING CONDITIONS(Ta=25ºC,PWMVdd=3.3V, DVdd=1.8V : Unless otherwise s

Rev.1.00 2003.05.08 page 5 of 23M65881AFPCHARACTERISTICS EVALUATION CIRCUITOUTR2OUTR1161718+-+--+M65881AFP3941OUTL1OUTL2-++-+--+24HPOUTL1HPOUTL2-++-3

Rev.1.00 2003.05.08 page 6 of 23M65881AFPPIN DESCRIPTIONPin No. Name I/OOutputCurrenton 3.3VSignal Level1 VddLPower Supply for Lch PWM Power Stage (3

Rev.1.00 2003.05.08 page 7 of 23M65881AFPEXPLANATION OF OPERATIONDATA,BCK, and LRCK are input pins for Digital Audio Signal of CD, MD, DVD etc..Input

Rev.1.00 2003.05.08 page 8 of 23M65881AFPSCDT, SCSHIFT and SCLATCH are input pins for setting M65881AFP's operation.Input format of SCDT, SCSHIF

Rev.1.00 2003.05.08 page 9 of 23M65881AFPFsoCKO is clock output pin of 1fso frequency. The output is divided-clock of XfsoIN, and frequencyis free-ru