Renesas HD49335HNP User Manual

Rev.1.0, Feb.12.2004, page 1 of 29 HD49335NP/HNP CDS/PGA & 10-bit A/D TG Converter REJ03F0097-0100Z Rev.1.0 Feb.12.2004 Description The HD4933

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 10 of 29 Timing Chart Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used. 012 91011

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 11 of 29 Detailed Timing Specifications Detailed Timing Specifications when CDSIN Input Mode is Used Figur

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 12 of 29 Detailed Timing Specifications at Pre-Blanking Figure 5 shows the pre-blanking detailed timing sp

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 13 of 29 Dummy Clamp It adjusts the mis-clamp which occurs when taking the photo under the highlight condi

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 14 of 29 Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Power supply voltage VDD 4.1 V An

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 15 of 29 Electrical Characteristics (cont.) (Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 16 of 29 Electrical Characteristics (cont.) (Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 17 of 29 Serial Interface Specifications Timing Specifications SDATASTD2(Upper data) STD1(Lower data) addr

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 18 of 29 Explanation of Serial Data of CDS Part Serial data of CDS part are assigned to address H’F0 to H’

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 19 of 29 • Output mode (D2 to D4 of address H’F1 and address H’F4 of D6) It is a test mode. Combination

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 2 of 29 Pin Arrangement 48 47 3946 45 44 43 42 41 40 38 36 35 343712 103 4 5 6 7 8 9 11 12 13 14 153231302

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 20 of 29 Address STD1[7:0] (L) STD2[15:8] (H)11110100 D4D3D2D7 D6 D5 D1 D0 D12 D11 D10 D9 D8Gray_testVD la

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 21 of 29 Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC outp

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 22 of 29 • Address H’F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page.

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 23 of 29 (3) Setting method of DLL 281401.2.3.42∗Default5610H1DLL step decides the how many divide the 1cy

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 24 of 29 Operation Sequence at Power On VDD(1) Resistor transfer of TG part(2) DLL data transfer of CDS pa

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 25 of 29 Timing Specifications of High Speed Pulse twotwhtrtwltwltf50%50%tH1DL90%10%90%10%H2RG• H1, H2, RG

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 26 of 29 Notice for Use 1. Careful handling is necessary to prevent damage due to static electricity. 2.

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 27 of 29 Example of Recommended External Circuit • Slave mode Pin 57(Test1 = Low)31343536373839404142434

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 28 of 29 • CDS single operating mode Pin 56(Test2 = Low) ∗Pin 57 is "Don't care" in this

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 29 of 29 Package Dimensions Package CodeJEDECJEITAMass (reference value)TNP-64AV——0.14 gUnit: mm1 90.20 ±

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 3 of 29 Pin Description (cont.) Pin No. Symbol Description I/O Analog(A) or Digital(D) Remarks 30 XV

Keep safety first in your circuit designs!1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more relia

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 4 of 29 Input/Output Equivalent Circuit Pin Name Equivalent Circuit D0 to D9, HD_in, VD_in, H1A, H2A, 1

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 5 of 29 Block Diagram 10bitADCAVSSVRBVRMVRTCDS_inCDSBLKSHBLKCADC_inSUB_SWSUB_PDSTROBD9D8D7D6D5D4D3D2D1D0Re

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 6 of 29 Internal Functions Functional Description • CDS input  CCD low-frequency noise is suppressed by

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 7 of 29 3. Automatic Offset Calibration Function and Black-Level Clamp Data Settings The DAC DC voltage a

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 8 of 29 6. ADC Digital Output Control Function The ADC digital output includes the functions output enabl

HD49335NP/HNP Rev.1.0, Feb.12.2004, page 9 of 29 7. Adjustment of Black-Level S/H Response Frequency Characteristics The CR time constant that is